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課程名稱 |
計算機結構
Computer Architecture |
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開課學期 |
109-2 |
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授課對象 |
電機工程學系 |
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授課教師 |
吳安宇 |
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課號 |
EE4039 |
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課程識別碼 |
901 43200 |
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班次 |
01 |
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學分 |
3.0 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期二7,8,9(14:20~17:20) |
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上課地點 |
電二144 |
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備註 |
總人數上限：40人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1092_CA |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
1. The basic concept of RISC (Reduced Instruction Set Computer), compared with CISC (Complex Instruction Set Computer)
2. The Assembly/Machine language of the MIPS CPU
3. Detailed CPU design:
Instruction set, Data path, Control Unit, Arithmetic Logic Unit (ALU),
Techniques to enhance CPU performance, e.g., pipelining and hazard control
4. Memory hierarchy:
Cache (L1$, L2$, etc.): How to improve data/instruction access time for CPU?
Virtual memory: How to handle program/data that is larger than your physical (main) memory?
5. I/O peripherals:
Know more about I/O Devices and Networking Devices
6. New trend of multi-core CPUs (overview)
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課程目標 |
Learn basic MIPS/RISC-V CPU architecture and Memory hierarchy of computer system. |
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課程要求 |
待補 |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
待補 |
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參考書目 |
1. David A. Patterson, and John L. Hennessy, “Computer Organization and Design – The Hardware/Software Interface”, 5th Edition (Asian edition), Morgan Kaufman Publishers, Inc., 2013.
2. (Verilog Coding, optional) “Verilog HDL: Digital design and modeling,” by J. Cavanagh, CRC Press, 2007.
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評量方式
(僅供參考) |
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週次 |
日期 |
單元主題 |
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第1週 |
2/23 |
- Syllabus
- Course overview |
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第2週 |
3/02 |
1. Computer v.s. IC Technology
2. Chap. 1 Computer Abstractions and Technology |
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第3週 |
3/09 |
Chap.2: Instructions: Language of the Computer
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第4週 |
3/16 |
W3_Chapter2-Part I v2.1 (minor updated)
W4_Chapter2-Part II v2.1 (minor updated) |
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第5週 |
3/23 |
Lab 1 |
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第6週 |
3/30 |
1. Homework using SPIM
2. W5 Chapter4-(1&2)-2021-03-30_v1.pdf |
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第7週 |
4/06 |
溫書假 can study
- Review of Single-cycle MIPS
- Review of Pipelined MIPS
Lectures are now in NTU COOL.
- Week 7 - 4/06
1. Review of Single-cycle MIPS (from DSD 2019)
2. Review of Pipelined MIPS - Part I (from DSD 2019)。
3. Review of Pipelined MIPS - Part II (from DSD 2019) |
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第8週 |
4/13 |
W8 Chapter4-(3)-2021-04-13 v1 (teach on 4/13)
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第9週 |
4/20 |
W8 Chapter4-(3)-2021-04-20 v1.1
W9 Chapter3-2021-04-20 v2 |
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第10週 |
4/27 |
Chap. 5: Memory hierarchy (Cache in CPU) |
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第11週 |
5/04 |
期中考 (closed book): 100 mins
5/4: 2:30pm-4:10pm
Exam covers Chap. 1-Chap. 4 (slides and lectures)
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第13週 |
5/18 |
Lab 2 slides
https://drive.google.com/file/d/1sO6frOc40AMCRjMdX-BHuxzHWxOhbAgV/view?usp=sharing |
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第14週 |
5/25 |
Chap.5 Memory hierarchy (Cache and VM)
Videos are now in NTU COOL |
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第15週 |
6/01 |
1. Chap. 5 (VM)
2. Chap. 6 (I/O & Storage) |
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第16週 |
6/08 |
Chap. 7 Multi-core/Multi-processor concept
New slide:
W16 Chapter 7 Multicores, Multiprocessors, and Clusters 2021-06-10 v3
Videos in COOL:
Part I: Evolution of Multicore/Manycore and Cache coherence
Part II: Software issues & Multi-threading
Part III: GPU/CUDA and Interconnection Network (Network-on-Chip, NoC)
CUDA slide from NTHU: "CUDA Programming" by Prof. Lee:
http://www.cs.nthu.edu.tw/~cherung/
http://www.cs.nthu.edu.tw/~cherung/teaching/2010gpucell/CUDA03.pdf
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第17週 |
6/15 |
Google Tensor Processing Unit (TPU) |
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第18週 |
6/22 |
Final exam |
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第19週 |
6/29 |
Final project report day |
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